Use of ASICs (application specific integrated circuits) has become widespread in the semiconductor industry as giving circuit design engineers a relatively high amount of functionality in a relatively small package. In particular, ASICs are customizable integrated circuits that are customized to implement a circuit specified by a design engineer (a “custom circuit design”). The term “ASIC” actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, gate arrays, and FPGAs. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate.
In forming ASICs generally, several layers will be required. FIG. 1 shows a partial cross-sectional view of a generic integrated circuit. First, active layers 110 are formed on a semiconductor substrate. The active layers 110 include devices such as transistors and diodes. Many active layer devices are formed independently of one another, i.e., they are not connected to form a circuit. Thus, once active layers 110 are formed, conducting layers, which are often composed of a metal such as aluminum or copper, are formed over the active layers to interconnect the devices, thereby forming a circuit. Several conducting layers may be required to completely interconnect the devices to form a useful circuit. Four conducting layers, M1 120, M2 130, M3 140, and M4 150, are shown in FIG. 1. Of course, different types of ICs or ICs fabricated using different processes may require more or less than four conducting layers for circuit interconnection.
In between each conducting layer is an insulating layer 115, 125, 135, 145 as shown in FIG. 1. Insulating layers are present to prevent shorts between conducting layers. To interconnect the conducting layers, vias 116 are formed through the insulating layers and are filled with conducting material (e.g., metal). Accordingly, the insulating layers are also sometimes referred to as “via layers.”
In forming the structure of FIG. 1, after the active layers 110 are formed, an insulating layer 115 is formed over the active layers 110, for instance, by growth or deposition of insulating material. Next, a masking step is utilized to form vias in the insulating layer, as is generally known in the art. Such masking often entails depositing a photoresist layer and patterning the layer using a mask and ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching the insulating layer in accordance with the photoresist pattern. After forming the vias, a conducting layer is deposited and then patterned using a similar masking process, so that metal (or other conductor) remains only in desired locations. The process is repeated for each insulating layer and conducting layer required to be formed.
Thus each conducting layer required to be formed generally demands at least two masking steps: one step to form vias through the insulating layer to connect to the layer below and one step to form connection wires or lines. Unfortunately, each mask step required generally entails significant time and expense. Moreover masks for vias generally cost twice as much as masks for conductor. Nonetheless, typical mask-programmed ASICs, such as gate arrays and standard cells, require a new mask design for each insulating and conducting layer.
One solution to minimizing both the time and monetary costs of customization is the FPGA (Field Programmable Gate Array). FPGAs utilize a predefined generic routing structure and is prefabricated through all layers. The routing structure is formed of a plurality of intersecting wires, many of which are coupled to vias to connect to lower layers. At each intersection is either a fuse or a programmable RAM bit. To customize the FPGA, either selected fuses are stressed to melt and form connections or the RAM bits are selectively programmed to form connections. Since the entire FPGA structure is fixed by the manufacturer, no additional mask steps are required and FPGA programming can actually be done by the IC designer with equipment and software at his or her own place of business. But despite rapid and easy customization, FPGAs currently available have drawbacks. FPGAs are often used in intermediate design steps for test purposes, but cannot often be used in a final product: because of the predefined nature of the FPGA routing structure and base array, an FPGA often will not meet the performance expectations of the final product (e.g., timing) and thus frequently has only limited use in test situations.
In sum, in implementing circuit designs with an ASIC, flexibility of design, rapid customization time, and low cost are all important considerations to the engineer using an ASIC. Therefore, any customizable circuit that can reduce customization time while minimizing costs is desirable.